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this is information on a product in full production. june 2012 doc id 14817 rev 4 1/44 1 stulpi01a, stulpi01b high-speed usb on-the-go ulpi transceiver datasheet ? production data features usb-if high-speed certified to the universal serial bus specification rev. 2.0 meets the requirements of the universal serial bus specification rev. 2.0, on-the-go supplement to the usb 2.0 specification 1.0a and ulpi transceiver specification 1.1 standard ulpi (utmi+ low pin interface) 1.1 digital interface fully compliant with ulpi 1.1 register set external square wave clock with v dvio amplitude must be applied to oscillator input xi supports 480 mbit/s high-speed, 12 mbit/s full-speed and 1.5 mbit/s low-speed modes of operation supports 2.7 v uart mode supports session request protocol (srp) and host negotiation protocol (hnp) for dual-role device features ability to control external charge pump for higher vbus currents single supply, +3 v to +4.5 v voltage range integrated dual voltage regulator to supply internal circuits with stable 3.3 v and 1.2 v integrated overcurrent detector integrated hs termination and fs/ls/otg pull-up/pull-down resistors integrated usb 2.0 ?short-circuit withstand? protection power-down mode with very low-power consumption for battery-powered devices ideal for system asics with built-in usb host, device or otg cores available in tfbga36 rohs package ?40 to 85 c operating temperature range applications mobile phones pdas mp3 players digital still cameras set-top box portable navigation devices description the stulpi01 is a high-speed usb 2.0 transceiver compliant with ulpi (utmi+ low pin interface) and otg (on-the-go) specifications, providing a complete physical layer solution for any high-speed usb host, device or otg dual- role core. it allows usb asics to interface with the physical layer of the usb through a 12-pin interface. it contains vbus comparators, an id line detector, usb differential drivers and receivers and a complete ulpi register map and interrupt generator. the stulpi01 transceiver is suitable for mobile applications and battery- powered devices because of its low-power consumption, power-down operating mode and minimal die/package dimensions. tfbga36 www.st.com
contents stulpi01a, stulpi01b 2/44 doc id 14817 rev 4 contents 1 application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 bump configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 oscillator and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 utmi + core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5 ulpi wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.6 external charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.7 vbus comparators and vbus overcurrent (oc) detector . . . . . . . . . . . . 19 6.8 vb_ref_fault pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.9 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.10 id detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.11 usb 2.0 phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.12 power saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.13 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.13.1 ulpi synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.13.2 6-pin fs/ls serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.13.3 3-pin fs/ls serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.14 car kit (uart) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.15 low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.16 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
stulpi01a, stulpi01b contents doc id 14817 rev 4 3/44 6.17 vio off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.18 startup procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.18.1 ulpi device detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.18.2 sdr mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.18.3 external clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.18.4 reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.18.5 interface protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.18.6 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.18.7 high-speed mode entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 ulpi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
list of tables stulpi01a, stulpi01b 4/44 doc id 14817 rev 4 list of tables table 1. bill of materials - external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. pinout and bump description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7. switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. high-speed driver eye pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9. vb_ref_fault configuration bit settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. car kit signals mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11. low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. usb state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13. ulpi register map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 14. register access legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 15. vendor and product id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 16. power control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 17. function control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 18. interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 19. otg control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 20. usb interrupt enable rising register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 21. usb interrupt enable falling register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 22. usb interrupt status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 23. usb interrupt latch register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 24. setting rules for interrupt latch register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 25. debug register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 26. scratch register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 27. car kit control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 28. tfbga36 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 29. tape and reel tfbga36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 30. order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 31. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
stulpi01a, stulpi01b list of figures doc id 14817 rev 4 5/44 list of figures figure 1. peripheral only, configuration with external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. high-speed driver eye pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4. rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. vb_ref_fault pin functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. usb 2.0 phy block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8. startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9. resetn behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 10. high-speed mode entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. uart mode entry (2.7 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 12. uart mode exit (2.7 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 13. tfbga36 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 14. tape and reel tfbga36 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
application diagrams stulpi01a, stulpi01b 6/44 doc id 14817 rev 4 1 application diagrams figure 1. peripheral only, configuration with external clock am04944v2 v dvio v dvio v dvio clk dir s tp nxt d[0]...d[7] re s etn c s n / pwrdn 3 v 3 v 1v2v vbat xi extern a l clock 19.2/26 mhz v dvio a mplit u tde xo id dp dm vbu s rref p s wn vb_ref_fault 5x gnd gnd high- s peed u s b-otg controller c f2 e1 e2 c f4 c f4 c f 3 open or gro u nd r bu s c t r ref c f1 mini-b d+ d- vbu s gnd b a ttery volt a ge table 1. bill of materials - external components qty. symbol value description 1c f1 0.1 - 1 f filtering capacitor. suggested components: murata 10 v x5r (grm188r61a105ka61) or murata 10 v y5v (grm188f51a105za01) or taiyo yuden 25 v x5r (tmk107bj105ka) 2c f4 0.1 - 1 f filtering capacitor. suggested components: murata 10 v x5r (grm188r61a105ka61) or murata 10 v y5v (grm188f51a105za01) or taiyo yuden 25 v x5r (tmk107bj105ka) 1c f2 1 f - 1.5 f filtering capacitor. suggested components: murata 10 v x5r (grm188r61a105ka61) or murata 10 v y5v (grm188f51a105za01) or taiyo yuden 25 v x5r (tmk107bj105ka) 1c f3 1 - 4.7 f filtering capacitor. suggested components: murata 10 v y5v (grm188f51a475ze20) or taiyo yuden 6.3 v x5r (jmk107bj475ka) 1c t 4.7 f tank capacitor 1r ref 12 k reference resistor 1% 1 e1 usbulc6-2f3 1 e2 esda14v2-2bf3 1r bus 2.2 k series overvoltage protection resistor
stulpi01a, stulpi01b bump configuration doc id 14817 rev 4 7/44 2 bump configuration figure 2. pin connections tfbga 3 6 (bottom view) a b c d e f 1 2 3 4 5 6 tfbga 3 6 (throu g h top s ide view) 6 5 4 3 2 1 d5 d4 clk d 3 d2 d1 a d6 1v 8 vio gnd 1v 8 vio 1v 8 vio d0 b d7 gnd re s etn c s n/ pwrdn rref dm c s tp nxt p s wn id gnd dp d 1v2v dir gnd 3 v 3 v vb_ref _fault gnd e xo xi vbu s vbat nc nc f 6 5 4 3 2 1 d 5 d5 d 4 d4 c l k clk d 3 d 3 d 2 d2 d 1 d1 a d 6 d6 gnd v dvio d 0 d0 b d 7 d7 gnd r e s e t n re s etn c s n/ p w r d n c s n/ pwrdn rr e f rref d m dm c s t p s tp n x t nxt p s wn p s wn i d id gnd d p dp d 1v2v d i r dir gnd 3 v 3 v v b _ r e f _ f a u lt vb_ref _fault gnd e xo xi v b u s t vbu s vbat nc nc f am04945v1 v dvio v dvio table 2. pinout and bump description bump symbol type description b1 d0 i/o data bit [0] (v dvio referred). uart txd signal. a1 d1 i/o data bit [1] (v dvio referred). uart rxd signal. a2 d2 i/o data bit [2] (v dvio referred). uart reserved pin. a3 d3 i/o data bit [3] (v dvio referred). uart active high interrupt indication. a4 clk o clock out (v dvio referred) a5 d4 i/o data bit [4] (v dvio referred) a6 d5 i/o data bit [5] (v dvio referred) b6 d6 i/o data bit [6] (v dvio referred) c6 d7 i/o data bit [7] (v dvio referred) d6 stp i ulpi stop signal (v dvio referred) d5 nxt o ulpi next signal (v dvi o referred) e5 dir o ulpi direction signal (v dvi o referred) c3 csn/pwrdn i chip select active low, power-down active high c4 resetn i active low asynchronous reset d1 dp i/o positive data line of the usb. 5 v tolerant. c1 dm i/o negative data line of the usb. 5 v tolerant. d3 id i id pin of the usb connector for initial device role selection. 5 v tolerant. f4 vbus i/o v bus line of the usb interface, requires an external capacitor of 4.7 f.
bump configuration stulpi01a, stulpi01b 8/44 doc id 14817 rev 4 bump symbol type description f1 nc not connected f2 nc not connected. e2 vb_ref_fault i voltage reference for internal oc detector input or digital input from external oc detector (v 3v3v referred). 5 v tolerant. d4 pswn o external charge pump control, active low. 5 v tolerant, open drain. f5 xi i external clock input (v dvio referred). f6 xo o xo pin must be left floating or grounded (crystal is not supported). f3 vbat pwr battery power input for the ldo (3 v ? 4.5 v). bypass v bat to gnd with a 1 f capacitor. e3 3v3v pwr 3.3 v ldo output. bypass 3v3v to gnd with a 1.5 f capacitor. e6 1v2v pwr 1.2 v ldo output. bypass 1v2v to gnd with a 1.5 f capacitor. c2 rref i/o reference resistor (12 k 1%) b2/b3/b5 v dvi o pwr digital i/o supply voltage. bypass each v dvi o to gnd with a 100 nf-1 f capacitor. balls b2-b5 can share common capacitor. c5/d2 gnd pwr ground b4/e4/e1 gnd pwr ground table 2. pinout and bump description (continued)
stulpi01a, stulpi01b maximum ratings doc id 14817 rev 4 9/44 3 maximum ratings note: absolute maximum ratings are those values above which damage to the device may occur. functional operation under these conditions is not implied. all voltages are referenced to gnd. table 3. absolute maximum ratings symbol parameter value unit v dvio digital i/o supply voltage -0.3 to +4.0 v v 1v2 digital core supply voltage (provided internally by ldo) -0.3 to +1.4 v v 3v3 analog supply voltage (provided internally by ldo) -0.3 to +4.0 v v bat battery supply voltage -0.3 to +7.0 v v dcdig dc voltage on digital pins (clk, dir, stp, nxt, d[0-7], resetn, xi, csn/pwrdn) -0.3 to +4.0 v v dcvbus dc voltage on 5 v tolerant pins (vbus,vb_ref_fault, dp, dm, id) -0.3 to +5.5 v t stg storage temperature range -40 to +125 c v esd-hbm electrostatic discharge voltage on all pins (according to jesd22-a114-b) 2.0 kv table 4. thermal data symbol parameter value unit r thja thermal resistance junction-ambient (simulated value as per jedec jsd51) 113.8 c/w r thjc thermal resistance junction-case (simulated value as per jedec jsd51) 47 c/w r thjb thermal resistance junction-base (simulated value as per jedec jsd51) 66.2 c/w table 5. recommended operating conditions symbol parameter min. typ. max. unit v bat battery supply voltage 3.0 3.6 4.5 v v dvio digital i/o supply voltage 1.65 1.80 3.6 v t a operating temperature range -40 +85 c c t tank capacitor 1 4.7 6.5 f r ref external reference resistor 11.88 12 12.12 k xtal external square wave (01a, 01b versions) 19.2 or 26 mhz recommended rise/fall time 4 ns
electrical characteristics stulpi01a, stulpi01b 10/44 doc id 14817 rev 4 4 electrical characteristics table 6. electrical characteristics symbol parameter test conditions (1) min. typ. max. unit power consumption i bat supply current active mode (usb bus idle) 15 ma active mode (fs transmission, 12 mb/s traffic) 30 ma active mode (hs transmission) 50 ma suspend mode (not including dp pull-up current, external clock stopped) 120 a uart mode (no transmission) 15 ma power-down mode 0.4 2 a vio off mode (v dvi o = 0) 0.4 2 a i dvio ulpi bus supply current v dvi o power-down mode 0.1 10 a active mode, 4 pf load 1.8 ma logic inputs and outputs c ulpiin ulpi port i/o capacitance 2.4 3.5 pf v oh high level output voltage (ulpi bus) i oh = -2 ma v dvio -0.15 v v ol low level output voltage (ulpi bus) i ol = +2 ma 0.15 v i ozh_pswn high level output leakage (pswn) v oh_pswn = 3.3 v power switch disabled 1.0 a v ol_pswn low level output voltage (pswn) i ol = +2 ma power switch enabled 0.15 v v ih high level input voltage (ulpi port and resetn) 0.65 x v dvio v v il low level input voltage (ulpi port and resetn) 0.35 x v dvio v i ih high level input leakage current v ih = v dvio -0.2 v 1.0 a
stulpi01a, stulpi01b electrical characteristics doc id 14817 rev 4 11/44 symbol parameter test conditions min. typ. max. unit i il low level input leakage cur- rent v il = 0.2 v 1.0 a v pdh high level input voltage (csn/pwrdn pin) v bat = 3.0 v to 4.5 v 1.4 v v pdl low level input voltage (csn/pwrdn pin) v bat = 3.0 v to 4.5 v 0.4 v i pdh high level input leakage current (csn/pwrdn pin) v pd = 1.4 v, v bat = 4.5 v 1.0 a i pdl low level input leakage current (csn/pwrdn pin) v pd = 0.4 v, v bat = 4.5 v 1.0 a v faulth high level input voltage (vb_ref_fault pin) overcurrent_pd bit is set 0.65 x v 3v3 v v fault l low level input voltage (vb_ref_fault pin) overcurrent_pd bit is set 0.15 x v 3v3 v r in_vb_ref vb_ref_fault pin input resistance 112 148 168 k v xi_hyst_ext external clock input hysteresis xo = ?0? at reset 500 mv v xih high level input voltage (xi pin) xo = ?0? at reset 0.65 x v dvio v v xil low level input voltage (xi pin) xo = ?0? at reset 0.15 x v dvio v vbus v bus_lkg v bus leakage voltage no load 200 mv r vbus v bus input impedance 40 100 k v bus_vld v bus valid comparator threshold 1 k series resistors 4.4 4.75 v v sess_vld session valid comparator threshold for both a and b device low to high transition 0.8 1.45 2.0 v high to low transition 1.25 v v sess_end session end comparator threshold 0.2 0.8 v r vbus_pu v bus charge pull-up resistance 650 950 1150 r vbus_pd v bus discharge pull-down resistance 800 1250 1500 table 6. electrical characteristics (continued)
electrical characteristics stulpi01a, stulpi01b 12/44 doc id 14817 rev 4 symbol parameter test conditions min. typ. max. unit overcurrent detector v oc overcurrent trip threshold vb_ref_fault ? vbus v oc = vb_ref_fault ? vbus 20 45 95 mv id i id_pu id pin pull-up current v id = 0 v 70 a r id_gnd id line short resistance to detect id gnd state 1k r id_float id line short resistance to detect id float state 100 k uart mode (2.7 v 5%) v oh_uart high level output voltage (d1, d3) i oh = -2 ma v dvio - 0.15 v v ol_uart low level output voltage (d1, d3) i ol = +2 ma 0.15 v v ih_uart_d0 high level input voltage (d0) 0.65 x v dvio v v il_uart_d0 low level input voltage (d0) 0.35 x v dvio v v oh_dfms high level output voltage (dp) i oh = -2 ma 2.16 2.85 v v ol_dfms low level output voltage (dp) i ol = +2 ma, pull-up = 10 k -0.10 0.37 v v ih_dtms high level input voltage (dm) 2.0 3.0 v v il_dtms low level input voltage (dm) -0.3 0.81 v full-speed/low-speed driver z drv output impedance (acting also as high-speed termination) 40.5 49.5 v oh_drv high level output voltage r lh = 14.25 k 2.8 3.6 v v ol_drv low level output voltage r ll = 1.425 k 0.0 0.3 v v crs driver crossover voltage c load = 50 to 600 pf (2) 1.3 1.67 2.0 v high-speed driver v hsoi hs idle level -10 10 mv v hsdpj hs data dp j state level (2) 380 440 mv v hsdk hs data dp k state level -10 10 mv table 6. electrical characteristics (continued)
stulpi01a, stulpi01b electrical characteristics doc id 14817 rev 4 13/44 symbol parameter test conditions min. typ. max. unit v hsdnj hs data dn j state level (2) 380 440 mv v hsdnk hs data dn k state level -10 10 mv v chirpj chirp j level (differential voltage) (2) 700 1100 mv v chirpk chirp k level (differential voltage -900 -500 mv full-speed/low-speed receivers v di diff. receiver input sensitivity (v dp -v dm ) v cm = 0.8 to 2.5 v 200 mv v se_th se receivers switching threshold low to high transition 0.8 1.6 2.0 v high to low transition 0.8 1.1 2.0 v r inp input resistance pu/pd resistors deactivated 300 k c in input capacitance (2) 5pf cin difference in capacitance between dp and dm input 10 % v dt_lkg data line leakage voltage r pu_ext = 300 k 342 mv high-speed receiver v hssq hs squelch detector threshold 100 150 mv v hsdsc hs disconnect detection threshold 525 625 mv v hscm hs data signaling common mode volt. range (2) -50 500 mv v hsterm termination voltage in hs (2) -10 10 mv data pull-up/pull-down resistors r pu data line pull-up resistance (dp, dm) 1.425 k v ihz fs idle high level voltage 2.7 v r pd data line pull-down resistance (dp, dm) 14.25 24.8 k voltage regulator 3v3v 3.3 v internal power supply voltage v bat = 3.6 v, active mode 3.26 3.4 3.54 v 1v2v 1.2 v internal power supply voltage v bat = 3.6 v, active mode 1.187 1.25 1.31 v 1. characteristics measured over recommended operating conditions unless otherwise noted. all typical values are referred to t a = 25 c, v dvio = 1.8 v, v bat = 3.6 v, r ref = 12 k ; c t = 4.7 f. 2. guaranteed by design. table 6. electrical characteristics (continued)
electrical characteristics stulpi01a, stulpi01b 14/44 doc id 14817 rev 4 table 7. switching characteristics symbol parameter test conditions (1) min. typ. max. unit reset t resetext width of reset pulse on resetn pin 10 s uart mode t rise switching time (max. low to min. high) c load = 185 pf 215 ns t fall switching time (min. high to max. low) c load = 185 pf 215 ns t pd_rx delay time (50% dm to 50% d1) c l = 10 pf 60 ns t pd_tx delay time (50% d0 to 50% dp) 60 ns t uarton2v7 turn-on time for txd line (2v7) uart_2v7 = 1 measured from dir assertion 22.5ms t uartoff2v7 turn-off time for txd line (2v7) uart_2v7 = 1 measured from stp assertion 1s t uarton turn-on time for txd line uart_2v7 = 0 measured from dir assertion 60 ns t uartoff turn-off time for txd line uart_2v7 = 0 measured from dir de-assertion 60 ns low-speed driver t lr data signal rise time c load = 600 pf 75 100 300 ns t lf data signal fall time c load = 600 pf 75 100 300 ns rfm ls rise and fall time matching -20 20 % dr ls low-speed data rate 1.49925 1.50075 mb/s t ddj1 data jitter to next transition includes freq. tolerances -25 25 ns t ddj2 data jitter for paired transitions includes freq. tolerances -14 14 ns t leopt se0 interval of eop 1250 1500 ns full-speed driver t fr data signal rise time c load = 50 pf 4 20 ns t ff data signal fall time c load = 50 pf 4 20 ns rfm fs rise and fall time matching -10 +10 % dr hs full-speed data rate 11.994 12.006 mb/s t dj1 data jitter to next transition includes freq. tolerances -3.5 3.5 ns t dj2 data jitter for paired transitions includes freq. tolerances -4 4 ns t feopt se0 interval of eop 160 175 ns clock generation constants t pll pll lock time (2) 200 s t dll dll lock time (2) 280 s
stulpi01a, stulpi01b electrical characteristics doc id 14817 rev 4 15/44 symbol parameter test conditions min. typ. max. unit high-speed driver t hsr data rise time 500 ps t hsf data fall time 500 ps waveform requirements including jitter specified by eye pattern ( figure 3 ) dr hs high-speed data rate 479.76 480.24 mb/s ulpi interface clock (measured on clk pin) f start_u frequency (first transition) (2) 54 60 66 mhz f steady_u frequency (steady-state) 59.97 60 60.03 mhz d start_u duty cycle (first transition) 40 50 60 % d steady_u duty cycle (steady-state) (2) 45 50 55 % t steady_u time to reach steady-state frequency and duty cycle after first transition (2) 1.4 ms t jitter_u jitter 400 ps t sclk60out clock startup time measured from assertion of stp during suspend, or after release of resetn pin 250 900 s ulpi control signals (sdr mode) (2) t sc_u control in setup time c load = 15 pf v dvio = 1.65 - 3.6 v 6.0 ns t hc_u control in hold time 0.0 ns t dc_u control output delay 9.0 ns ulpi data signals (sdr mode) (2) t sd_u data in setup time c load = 15 pf v dvio = 1.65 - 3.6 v 6.0 ns t hd_u data in hold time 3.0 ns t dd_u data output delay 9.0 ns 1. over recommended operating conditions unless otherwise noted. all the typical values are referred to t a = 25 c, v dvio = 1.8 v, v bat = 3.6 v, c t = 4.7 f. 2. guaranteed by design. table 7. switching characteristics (continued)
electrical characteristics stulpi01a, stulpi01b 16/44 doc id 14817 rev 4 figure 3. high-speed driver eye pattern +400 mv differenti a l -400 mv differenti a l 0 v differenti a l level 1 level 2 point 1 point 2 point 3 point 4 point 5 point 6 % 0 0 1 % 0unit interv a l am04946v2 table 8. high-speed driver eye pattern parameter level 1 level 2 point 1 point 2 point 3 point 4 point 5 point 6 voltage level (dp ? dm) 525 mv (1) 475 mv ?525 mv (1) ?475 mv 0 v 0 v 300 mv 300 mv ?300 mv ?300 mv time (% of unit interval) 5% 95% 35% 65% 35% 65% 1. this value is valid for unit intervals following a transition. for all other intervals the other value is valid.
stulpi01a, stulpi01b timing diagram doc id 14817 rev 4 17/44 5 timing diagram figure 4. rise and fall time figure 5. simplified block diagram 90% 10% r t ol_drv v t f 90% 10% oh_drv v c s 260 8 0 ulpi o s cill a tor pll power on re s et u s b 2.0 phy utmi + interface xi xo clk dir s tp nxt d0 - d7 v dvio vbu s re s etn dp dm id p s wn gnd d ua l volt a ge reg u l a tor vbat gnd volt a ge reference utmi + core otg block ch a rge p u mp, vbu s comp a r a tor s id detector vb_ref_fault over- c u rrent f au lt detector rref ulpi wrapper a nd pll u s b 2.0 phy utmi + interface id utmi + core otg block ch a rge p u mp, vbu s comp a r a tor s id detector am04947v2
block description stulpi01a, stulpi01b 18/44 doc id 14817 rev 4 6 block description the stulpi01 integrates a comparator for the vbus, id line detector, differential hs data driver, differential and single-ended receivers, low dropout voltage regulators, and control logic. the stulpi01 provides a complete solution for the connection of a digital usb host/device/otg controller to a usb bus. 6.1 oscillator and pll an external clock (digital square wave v dvio referred) driven into xi must be used (version stulpi01a or stulpi01b). the pll internally produces all frequencies needed for operation: 60-mhz clock for the utmi core and ulpi interface controller 1.5 mhz for low-speed usb data 12 mhz for full-speed usb data 480 mhz for high-speed usb data other internal frequencies for data conversion and data recovery. 6.2 voltage reference this block provides the precise reference voltage needed by the internal circuit. it requires a 12 k +/- 1% resistor connected to the r ref pin. 6.3 power-on reset (por) the power-on reset circuit generates a reset pulse upon power-up which is used to initialize the entire digital logic. power-on reset senses the v 3v3v and v 1v2v voltage. during the power-on reset pulse, the ulpi pins are in a high impedance state with pull- down/pull-up resistors disabled. 6.4 utmi + core this is the digital heart of the chip and performs the bit-stuffing, nrzi decoding and serial to parallel conversion during receive and the reverse operation during transmit for hs and fs/ls. 6.5 ulpi wrapper this implements the ulpi related protocol and conversion from utmi+ to ulpi interface. this block also implements the interrupt logic and complete ulpi register set.
stulpi01a, stulpi01b block description doc id 14817 rev 4 19/44 6.6 external charge pump it is possible to use an external charge pump or power switch controlled by the pswn pin (active low open drain). this functionality is controlled by drvvbus and drvvbusexternal ulpi otg control register bits. 6.7 v bus comparators and v bus overcurrent (oc) detector these comparators monitor the v bus voltage. v bus valid status signals that the voltage is above the v bus_vld level (4.4 v). session valid status signals that the v bus voltage is above the v sess_vld level (0.8 to 2.0 v). session end detector signals that v bus voltage is below v sess_end level. the stulpi01 also implements an embedded v bus overcurrent detector which compares v bus voltage to the external analog 5 v reference signal applied to the vb_ref_fault pin. 6.8 vb_ref_fault pin v bus overcurrent conditions can be monitored by either an internal or external oc detector. the internal oc detector is enabled when the overcurrent_pd bit in the power control register (vendor-specific area) is set to 0b and use external vbus indicator is set to 1b. in this mode, the vb_ref_fault pin functions as the input of the analog reference for internal overcurrent detector. if the external charge pump is already equipped with an overcurrent detector, its output can be also monitored through the vb_ref_fault pin, but the overcurrent_pd bit must be set to 1b. in this mode, vb_ref_fault functions as the standard digital input pin with 5 v tolerance. functionality of the vb_ref_fault pin can be seen in more detail in figure 6 . note: after reset, the overcurrent_pd bit is 1b, the internal overcurrent detector is disabled.
block description stulpi01a, stulpi01b 20/44 doc id 14817 rev 4 figure 6. vb_ref_fault pin functionality 6.9 voltage regulator the dual output ultra low dropout voltage regulator provides the power supply for analog and digital internal circuits. an external capacitor on both the 3v3v and 1v2v pins is needed for proper operation. 6.10 id detector this block provides the sensing of the status of the id line. it is capable of detecting whether the pin is floating or tied to the ground. 6.11 usb 2.0 phy the usb 2.0 phy block provides a complete physical layer transceiver for low-speed, full- speed, and high-speed usb operating modes. the analog part of this block deals with impedance adaptation, controlled voltage swing, and common mode voltage generation + - ref vbref_fault intern a l vbu s v a lid vbu s vld [u s eextern a lv bus indic a tor, indic a torp ass thr u ] rx cmd vbu s v a lid 2 0 1 [0,x] [1,0] [1,1] bu s vb ref v bu s (5 v tolerant) vbu s fault + - vboc en /en + - v a lid indic a torcomplement overc u rrent_pd or neg (u s eextern a lv bus indic a tor) 0 1 [0,x] [1,1] v v vbu s + - vboc r in_vbref + - ref vbref_fault intern a l vbu s v a lid vbu s vld [u s eextern a lv bus indic a tor, indic a torp ass thr u ] rx cmd vbu s v a lid 2 0 1 [0,x] [1,0] [1,1] bu s vb ref v bu s s chmitt (5 v tolerant) vbu s fault + - vboc en /en + - v a lid indic a torcomplement overc u rrent_pd or neg (u s eextern a lv bus indic a tor) 0 1 [0,x] [1,1] v v vbu s + - vboc r in_vbref am0494 8 v2 table 9. vb_ref_fault configuration bit settings rx cmd vbus valid use external vbus indicator overcurrent_pd indicator pass-thru indicator complement vbusvld 0 1 x x vboc 1 0 1 x vboc and vbusvld 1 0 0 x neg (fault) 1 1 1 0 fau lt 1 1 1 1 vbusvld and fault 1 1 0 1 vbus_vld and neg (fault) 1 1 0 0
stulpi01a, stulpi01b block description doc id 14817 rev 4 21/44 and sensing. the digital part consists of a serializer and deserializer, transforming serial bit stream to 8-bit parallel port, and finite state machine implementing the phy protocol layer, bit stuffing, unstuffing, etc. figure 7. usb 2.0 phy block diagram 6.12 power saving features to reduce power consumption, the stulpi01 implements 2 low-power modes of operation. 1. low-power mode, which is defined in the ulpi specification. 2. power-down mode to save more power in case usb function is not needed. more information on these modes can be found in the following paragraphs. 6.13 modes of operation 6.13.1 ulpi synchronous mode the stulpi01 transceiver supports sdr mode operation (12-pin interface). the selection of sdr mode is performed during the startup reset procedure. 6.13.2 6-pin fs/ls serial mode this mode is entered by writing to the corresponding bit in the interface control register. 6.13.3 3-pin fs/ls serial mode this mode is entered by writing to the corresponding bit in the interface control register. h s s er-de s l s /f s s er-de s h s di s connect det. squ elch detector l s /f s s e receiver s 3 . 3 v 3 . 3 v 19.25 k dp dn am04949v2
block description stulpi01a, stulpi01b 22/44 doc id 14817 rev 4 6.14 car kit (uart) mode this mode is entered by writing to the car kit mode bit in the interface control register. the stulpi01 does not implement all features of car kit mode, only the uart functionality is preserved. txd or rxd paths are activated only when the corresponding bits txd_en/rxd_en in car kit control register bits ( ta b l e 2 3 ) are set. the uart_2v7 bit controls the voltage level of uart signaling. if 2v7 volt signaling is used, after the uart mode is entered, pll is disabled and the voltage on the regulator output starts to decrease to 2.7 v. after a time marked as t uarton2v7 , the txd output on the usb bus is enabled. when leaving car kit mode, txd is disabled immediately when the stp pin is asserted. the time required to exit car kit mode is equivalent to the time needed for pll startup. when 3.3 volt uart signaling is selected, the txd line is enabled immediately after entering car kit mode, and disabled after exiting this mode. note: when car kit mode is used with 2v7 signaling, the pll and output clock are always stopped regardless of the setting of the clocksuspendm bit. 6.15 low-power mode the stulpi01 enters low-power mode when the suspendm bit in the interface control register is set to 0b. most of the references are turned off, pll and clock are turned off, but the full wake-up capability as defined in the ulpi specification is still maintained. when in low-power mode, the phy drives d3-d0 with the signals listed in table 11 . line state is driven combinatorially from the se receivers. the int signal is asserted whenever any unmasked interrupt occurs. the phy latches interrupt events directly from analog circuitry because the clock is powered down. table 10. car kit signals mapping default car kit signals mapping (uart_dir = 0) signal ulpi lines usb lines txd data[0] (input) -> dm (output) rxd data[1] (output) <- dp (input) reserved data[2] (input) int data[3] (output) car kit signals mapping (uart_dir = 1) signal ulpi lines usb lines txd data[0] (input) -> dp (output) rxd data[1] (output) <- dm (input) reserved data[2] (input) int data[3] (output)
stulpi01a, stulpi01b block description doc id 14817 rev 4 23/44 low-power mode is exited by asserting the stp pin high. pll is started immediately, and when the clock becomes stable, it is passed on the output of the clk pin. then, after a minimum of 5 clock cycles, dir is deas serted and low-power mode is exited. the suspendm bit is reset to 1b. note: the stp signal must be kept high until the dir is deasserted, otherwise low-power mode is not exited. 6.16 power-down mode power-down mode is entered by asserting the csn/pwrdn pin high. internal voltage regulators are disabled, and the device has minimum possible power consumption. the stulpi01 has no wake-up capa bility or usb functionality during power-down mode. this mode can be exited by deasserting the csn/pwrdn pin. voltage regulators are turned on and the internal power-on reset circuit resets the chip to initial state. ulpi interface pins are in high impedance state during power-down mode. 6.17 vio off mode if v dvio is below the minimum value, vio off mode is entered. the behavior of the device in vio off mode is the same as in power-down mode. 6.18 startup procedure 6.18.1 ulpi device detection the link detects ulpi device presence by sampling the dir signal at the reset time ( figure 8 ). the nxt signal is '0' after reset to signal an 8-bit device to the link controller. clk is '1' to signal a ddr capable device. 6.18.2 sdr mode selection the stulpi01 samples the d0 line on the first rising edge of the output clock on the clk pin. when the sampled value is '0', the stulpi01 remains in sdr mode. sdr mode can be selected again only after hardware reset. during software reset mode, selection is not performed. table 11. low-power mode signal map to dir description linestate (0) d0 out driven combinatorially from se receivers linestate (1) d1 out driven combinatorially from se receivers reserved d2 out reserved int d3 out active high interrupt indication. asserted whenever any unmasked interrupt occurs.
block description stulpi01a, stulpi01b 24/44 doc id 14817 rev 4 note: important: the controller must not drive the data lines to a value other than 0x00 or 0x01 during the first rising edge of ulpi clk, otherwise the behavior of the device may be undefined. 6.18.3 external clock detection the square wave clock can be applied to the oscillator input. the input square wave clock amplitude is referenced to v dvi o . the xo pin can be left floating or grounded. 6.18.4 reset behavior a typical startup sequence is shown in figure 12 . the stulpi01 contains an internal power-on reset generator which senses the v3v3v and v1v2v voltage. assertion of resetn is not necessary for proper initialization. however, if required, this pin can be also used. the internal reset signal is the combination of the signal from the resetn pin and the signal from the internal power-on reset circuit. when resetn is asserted, all internal registers are reset to their default values, the output dir signal is driven to '1', and data lines are pulled low by weak pull-downs. during reset, the stp pin can be driven low, high, or can be left floating. it is pulled up by internal pull-up and the ulpi interface enters a holding state. during the reset state, the nxt signal is driven low and the clk is driven high. when the pll is stabilized, the clock on the clk pin is enabled, and dir is deasserted. note: the minimum duration of the external reset signal is tr esetext. (see ta b l e 7 ). when internal por reset is asserted, the reset procedure is equivalent to the resetn signal, with the only exception being that the ulpi lines are in high impedance state. all pull- downs and pull-ups on the ulpi signals are also disabled. 6.18.5 interface protection the stulpi01 activates weak pull-downs on data lines and pull-up on the stp during reset and holding state. these are to provide interface protection during startup and anytime the link is not able to drive the ulpi lines properly. the holding state is entered when the controller drives the stp for more than 1 clock cycle. any command on the ulpi bus is ignored in this state. for more information see ulpi specification 1.1, section 3.12 (safeguarding phy input signals). interface protection can be switched off at any time after startup in order to save power, by writing the interface protect disable bit in the interface control register to 1b. 6.18.6 software reset the stulpi01 supports software reset by writing the reset bit in the function control register to 1b. during software reset, dir is asserted and the pull-down resistors on data lines are enabled, but the ulpi registers remain unaffected. software reset initializes utmi core logic only. also, during software reset, external clock detection, sdr mode selection is not performed, and the clock is not turned off (pll is not restarted).
stulpi01a, stulpi01b block description doc id 14817 rev 4 25/44 note: software reset is not required in the startup procedure for the stulpi. the chip is ready for operation after the hardware reset procedure. 6.18.7 high-speed mode entry in high-speed mode, the internal 480-mhz clock is generated by the dll, which must be calibrated any time the device enters high-speed mode by writing '00' to the xcvrsel field in the function control register. during the dll calibration, it is not possible to accept any commands, therefore, to avoid any communication problems with the controller, the clock on the ulpi interface is stopped. see figure 10 for more information. figure 8. startup sequence
block description stulpi01a, stulpi01b 26/44 doc id 14817 rev 4 figure 9. resetn behavior figure 10. high-speed mode entry am04951v1
stulpi01a, stulpi01b block description doc id 14817 rev 4 27/44 figure 11. uart mode entry (2.7 v) figure 12. uart mode exit (2.7 v)
state transitions stulpi01a, stulpi01b 28/44 doc id 14817 rev 4 7 state transitions table 12. usb state transitions signaling mode register settings resistor settings xcvrselect termselect opmode dppulldown dmpulldown rpu_dp_en rpu_dm_en rpd_dp_en rpd_dm_en hsterm_en general settings 3-state drivers xxb xb 01b 0b 0b 0b 0b 0b 0b 0b 3-state drivers with pull-down enabled xxb xb 01b 1b 1b 0b 0b 1b 1b 0b power-up or v bus < v th(sessend) 01b 0b 00b 1b 1b 0b 0b 1b 1b 0b host settings host chirp 00b 0b 10b 1b 1b 0b 0b 1b 1b 1b host high-speed 00b 0b 00b 1b 1b 0b 0b 1b 1b 1b host full-speed x1b 1b 00b 1b 1b 0b 0b 1b 1b 0b host hs/fs suspend 01b 1b 00b 1b 1b 0b 0b 1b 1b 0b host hs/fs resume 01b 1b 10b 1b 1b 0b 0b 1b 1b 0b host low-speed 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b host low-speed suspend 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b host low-speed resume 10b 1b 10b 1b 1b 0b 0b 1b 1b 0b host test_j/test_k 00b 0b 10b 1b 1b 0b 0b 1b 1b 1b peripheral settings peripheral chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b 0b peripheral high-speed 00b 0b 00b 0b 0b 0b 0b 0b 0b 1b peripheral full-speed 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b peripheral hs/fs suspend 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b peripheral hs/fs resume 01b 1b 10b 0b 0b 1b 0b 0b 0b 0b peripheral low-speed 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b peripheral low-speed suspend 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b peripheral low-speed resume 10b 1b 10b 0b 0b 0b 1b 0b 0b 0b peripheral test_j/test_k 00b 0b 10b 0b 0b 0b 0b 0b 0b 1b
stulpi01a, stulpi01b state transitions doc id 14817 rev 4 29/44 signaling mode register settings resistor settings xcvrselect termselect opmode dppulldown dmpulldown rpu_dp_en rpu_dm_en rpd_dp_en rpd_dm_en hsterm_en otg device, peripheral chirp 00b 1b 10b 0b 1b 1b 0b 0b 1b 0b otg device, peripheral high-speed 00b 0b 00b 0b 1b 0b 0b 0b 1b 1b otg device, peripheral full-speed 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b otg device, peripheral hs/fs suspend 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b otg device, peripheral hs/fs resume 01b 1b 10b 0b 1b 1b 0b 0b 1b 0b otg device, peripheral, test_j/test_k 00b 0b 10b 0b 1b 0b 0b 0b 1b 1b table 12. usb state transitions (continued)
ulpi registers stulpi01a, stulpi01b 30/44 doc id 14817 rev 4 8 ulpi registers table 13. ulpi register map overview field name size (bits) address (6 bits) rd wr set clr immediate register set vendor id low 8 00h - - - vendor id high 8 01h - - - product id low 8 02h - - - product id high 8 03h - - - function control 8 04-06h 04h 05h 06h interface control 8 07-09h 07h 08h 09h otg control 8 0a-0ch 0ah 0bh 0ch usb interrupt enable rising 8 0d-0fh 0dh 0eh 0fh usb interrupt enable falling 8 10-12h 10h 11h 12h usb interrupt status register 8 13h - - - usb interrupt latch register 8 14h - - - debug 8 15h - - - scratch 8 16-18h 16h 17h 18h car kit control register 8 16-1bh 19h 1ah 1bh reserved 8 1c-2eh access extended register set (see table 14 )8-2fh-- reserved 8 30-3ch power control 3d-3fh extended register set address (8 bits) maps to immediate register set above 8 00-3fh reserved 8 40-ffh table 14. register access legend access code expanded name meaning rd read register can be read. read-only if this is the only mode given. wr write pattern on the data bus is written over all bits of the register. sset pattern on the data bus is or?d with the register value and written into the register. c clear pattern on the data bus is a mask. if a bit in the mask is set, then the corresponding register bit is set to zero (cleared).
stulpi01a, stulpi01b ulpi registers doc id 14817 rev 4 31/44 note: 3dh-3fh(read), 3dh(write), 3eh(set), 3fh(clear). these addresses control various power aspects of the usb transceiver. table 15. vendor and product id register bits access address value description vendor_id_low 7:0 rd 00h 83 h lower byte of vendor id. vendor_id_high 7:0 rd 01h 04 h upper byte of vendor id. product_id_low 7:0 rd 02h 4b h lower byte of product id number. product_id_high 7:0 rd 03h 4f h upper byte of product id number. table 16. power control register field name bits access reset description reserved 0 rd/wr/s/c 0b reserved. the link must never write a 1b to this bit. overcurrent_pd 1 rd/wr/s/c 1b power control of the internal overcurrent circuit. 0b: enables the overcurrent circuit. 1b: disables the overcurrent circuit. uart_dir 2 rd/wr/s/c 0b 0b: txd on dm and rxd on dp 1b: txd on dp and rxd on dm uart_2v7 3 rd/wr/s/c 1b 0b: uart signaling at 3v3 1b: uart signaling at 2v7 reserved 7:4 rd/wr/s/c 0b reserved. the link must never write a 1b to these bits.
ulpi registers stulpi01a, stulpi01b 32/44 doc id 14817 rev 4 note: 04h-06h(read), 04h(write), 05h(set), 06h(clear). these addresses control utmi function setting of the usb transceiver phy. table 17. function control register field name bits access reset description xcvrselect 1:0 rd/wr/s/c 01b selects the required transceiver speed. 00b: enables hs transceiver 01b: enables fs transceiver 10b: enables ls transceiver 11b: enables fs transceiver for ls packets (fs preamble is automatically pre-pended) important note : every time xcvrselect is changed to ?00?, the output ulpi clock is stopped for the time needed for internal dll calibration. termselect 2 rd/wr/s/c 0b controls the internal pull-up resistors or hs terminations. control over these resistors changes depending on xcvrselect, opmode, dppulldown and dmpulldown, as shown in ta b l e 2 4 . opmode 4:3 rd/wr/s/c 00b selects the required bit encoding style during transmit. 00b: normal operation 01b: non-driving 10b: disables bit-stuff and nrzi encoding 11b: does not automatically add sync and eop when transmitting. must be used only for hs packets. reset 5 rd/wr/s/c 0b active high transceiver reset. after the link sets this bit, the stulpi01 asserts dir and reset the utmi+ core. when the reset is complete, the stulpi01 de-asserts dir and automatically clears this bit. after de-asserting dir, the stulpi01 re-asserts dir and sends an rx cmd update to the link. note : if reset bit is set to ?1? and suspendm bit is set to ?0? in the same register access, suspendm bit takes higher priority and the chip enters low-power mode. reset bit is cleared. suspendm 6 rd/wr/s/c 1b active low phy suspend. puts phy into low-power mode. the stulpi01 automatically sets this bit to ?1? when low-power mode is exited. 0b: low-power mode 1b: powered note: if reset bit is set to ?1? and suspendm bit is set to ?0? in the same register access, suspendm bit takes higher priority and the chip enters low-power mode. reset bit is cleared. reserved 7 rd/wr/s/c 0b reserved
stulpi01a, stulpi01b ulpi registers doc id 14817 rev 4 33/44 note: 07h-09h(read), 07h(write), 08h(set), 09h(clear). these addresses enable alternative interfaces and stulpi01 features. table 18. interface control register field name bits access reset description 6-pin fslsserialmode 0 rd/wr/s/c 0b changes the ulpi interface to 6-pin serial mode. the stulpi01 automatically clears this bit when serial mode is exited. 0b: fs/ls packets are sent using parallel interface. 1b: fs/ls packets are sent using 6-pin serial interface. 3-pin fslsserialmode 1 rd/wr/s/c 0b changes the ulpi interface to 3-pin serial mode. the stulpi01 automatically clears this bit when serial mode is exited. 0b: fs/ls packets are sent using parallel interface. 1b: fs/ls packets are sent using 4-pin serial interface. carkit mode 2 rd/wr/s/c 0b the stulpi01 does not support all the features of car kit mode. only the uart functionality is implemented. 0b: disables serial car kit mode. 1b: enables serial car kit mode. clocksuspendm 3 rd/wr/s/c 0b active low clock suspend. valid only in serial mode and car kit mode. powers down the internal clock circuitry. valid only when suspendm = 1b. the stulpi01 ignores clocksuspend when suspendm = 0b. by default, the clock is not powered in serial and car kit modes. 0b: clock is not powered in serial and car kit modes. 1b: clock is powered in serial and car kit modes. reserved 4 rd/wr/s/c 0b the stulpi01 does not implement auto-resume feature, because the clock can be restarted in less than 1ms. indicator complement 5 rd/wr/s/c 0b gives the command to invert the externalvbusindicator signal, generating the complement output. 0b: the stulpi01 does not invert externalvbusindicator signal 1b: stulpi01 inverts externalvbusindicator signal. indicator passthru 6 rd/wr/s/c 0b controls whether the complement output is qualified with the internal vbusvalid comparator before being used in the vbus state in the rx cmd. 0b: complements output signal is qualified with the internal vbusvalid comparator. 1b: complements output signal is not qualified with the internal vbusvalid comparator. interface protect disable 7 rd/wr/s/c 0b controls circuitry for protecting the ulpi interface when the link 3-states stp and data. this bit is not intended to affect the operation of the holding state. refer to section 3.12 of ulpi specification 1.1 for more details. 0b: enables the interface protection circuit (default). 1b: disables the interface protection circuit. interface protection circuit consists of pull-down resistors on data and pull-up resistors on stp.
ulpi registers stulpi01a, stulpi01b 34/44 doc id 14817 rev 4 note: 0ah-0ch(read), 0ah(write), 0bh(set), 0ch(clear). these addresses control utmi + otg functions of the phy. table 19. otg control register field name bits access reset description idpullup 0rd/wr/s/c0b connects a pull-up to the id line and enables sampling of the signal level. 0b: disables sampling of id line. 1b: enables sampling of id line. dppulldown 1rd/wr/s/c1b enables the 15 k pull-down resistor on dp. 0b: pull-down resistor not connected to dp. 1b: pull-down resistor connected to dp. dmpulldown 2rd/wr/s/c1b enables the 15 k pull-down resistor on dm. 0b: pull-down resistor not connected to dm. 1b: pull-down resistor connected to dm. dischrgvbus 3rd/wr/s/c0b discharges v bus through a resistor. if the link sets this bit to 1, it waits for an rx cmd indicating sessend has transition from 0 to 1, and then resets this bit to 0 to stop the discharge. 0b: does not discharge v bus 1b: discharges v bus chrgvbus 4rd/wr/s/c0b charges v bus through a resistor. used for v bus pulsing srp. 0b: does not charge v bus 1b: charges v bus drvvbus 5rd/wr/s/c0b signals the internal charge pump or external supply to drive 5 v on v bus . 0b: does not drive v bus (default) 1b: drives 5 v on v bus drvvbus external 6rd/wr/s/c0b selects between the internal and the external 5 v v bus supply. 0b: drives v bus using the internal charge pump (default). 1b: drives v bus using external supply. useexternal vbusindicator 7rd/wr/s/c0b tells stulpi01 to use an external v bus overcurrent indicator. 0b: uses the internal otg comparator or internal v bus valid indicator (default) 1b: uses external v bus valid indicator signal
stulpi01a, stulpi01b ulpi registers doc id 14817 rev 4 35/44 note: 0dh-0fh(read), 0dh(write), 0eh(set), 0fh(clear). if set, the bits in this register cause an interrupt event notification to be generated when the corresponding phy signal changes from low to high. by default, all transitions are enabled. rxactive and rxerror must always be communicated immediately and so are not included in this register. interrupt circuitry can be powered down in any mode when both rising and falling edge enables are disabled. to ensure interrupts are detectable when clock is powered down, the link should enable both rising and falling edges. table 20. usb interrupt enable rising register field name bits access reset description host disconnect rise 0 rd/wr/s/c 1b generates an interrupt event notification when host disconnect changes from low to high. applicable only in host mode (dppulldown and dmpulldown both set to 1b). vbusvalid rise 1 rd/wr/s/c 1b generates an interrupt event notification when vbusvalid changes from low to high. sessvalid rise 2 rd/wr/s/c 1b generates an interrupt event notification when sessvalid changes from low to high. sessvalid is the same as utmi+avalid. sessend rise 3 rd/wr/s/c 1b generates an interrupt event notification when sessend changes from low to high. id rise 4 rd/wr/s/c 1b generates an interrupt event notification when id changes from low to high. id is valid 50 ms after idpullup is set to 1b, otherwise id is undefined and should be ignored. reserved 7:5 rd/wr/s/c 0b reserved.
ulpi registers stulpi01a, stulpi01b 36/44 doc id 14817 rev 4 note: address 10h-12h(read), 10h(write), 11h(set), 12h(clear). if set, the bits in this register cause an interrupt event notification to be generated when the corresponding phy signal changes from high to low. by default, all transitions are enabled. rxactive and rxerror must always be communicated immediately and so are not included in this register. interrupt circuitry can be powered down in any mode when both rising and falling edge enables are disabled. to ensure interrupts are detectable when clock is powered down, the link should enable both rising and falling edges. note: address 13h(read-only). these bits indicate the current value of the interrupt source signal. interrupt circuitry can be powered down in any mode when both rising and falling edge enables are disabled. to ensure interrupts are detectable when clock is powered down, the link should enable both rising and falling edges. table 21. usb interrupt enable falling register field name bits access reset description host disconnect fall 0 rd/wr/s/c 1b generates an interrupt event notification when the host disconnect changes from high to low. applicable only in host mode. vbusvalid fall 1 rd/wr/s/c 1b generates an interrupt event notification when vbusvalid changes from high to low. sessvalid fall 2 rd/wr/s/c 1b generates an interrupt event notification when sessvalid changes from high to low. sessvalid is the same as utmi+avalid. sessend fall 3 rd/wr/s/c 1b generates an interrupt event notification when sessend changes from high to low. id fall 4 rd/wr/s/c 1b generates an interrupt event notification when id changes from high to low. id is valid 50 ms after idpullup is set to 1b, otherwise id is undefined and should be ignored. reserved 7:5 rd/wr/s/c 0b reserved table 22. usb interrupt status register field name bits access reset description host disconnect 0rd 0b current value of utmi+host disconnect output. applicable only in host mode. automatically reset to 0b when low-power mode is entered. vbusvalid 1 rd 0b current value of utmi+vbusvalid output. sessvalid 2rd 0b current value of utmi+sessvalid output. sessvalid is the same as utmi+avalid. sessend 3 rd 0b current value of utmi+sessend output. id 4rd 0b current value of utmi+id output. id is valid 50 ms after idpullup is set to 1b, otherwise id is undefined and should be ignored. reserved 7:5 rd 0b reserved
stulpi01a, stulpi01b ulpi registers doc id 14817 rev 4 37/44 note: address 14h(read-only with auto-clear). these bits are set by the stulpi01 when an unmasked change occurs on the corresponding internal signal. the stulpi01 automatically clears all bits when the link reads this register, or when low-power mode is entered. the stulpi01 also clears this register when serial mode or car kit mode is entered regardless of the value of clocksuspendm. the interrupt circuitry is powered down in any mode when both rising and falling edge enables are disabled. to ensure the interrupts are detectable when the clock is powered down, the link should enable both rising and falling edges. the stulpi01 follows the rules in ta bl e 2 0 for setting any latch register bit. it is important to note that if the register read data is returned to the link in the same cycle that a usb interrupt latch bit is to be set, the interrupt condition is given immediately in the register read data and the latch bit is not set. note that it is optional for the link to read the usb interrupt latch register in synchronous mode because the rx cmd byte already indicates the interrupt source directly. table 23. usb interrupt latch register field name bits access reset description host disconnect latch 0rd 0b set to 1b by the stulpi01 when an unmasked event occurs on host disconnect. cleared when this register is read. applicable only in host mode. vbusvalid latch 1rd 0b set to 1b by the stulpi01 when an unmasked event occurs on vbusvalid. cleared when this register is read. sessvalid latch 2rd 0b set to 1b by the stulpi01 when an unmasked event occurs on sessvalid. cleared when this register is read. sessvalid is the same as utmi+avalid. sessend latch 3rd 0b set to 1b by the stulpi01 when an unmasked event occurs on sessend. cleared when this register is read. id latch 4rd 0b set to 1b by the stulpi01 when an unmasked event occurs on id. cleared when this register is read. id is valid 50 ms after id is set to 1b, otherwise id is undefined and should be ignored. reserved 7:5 rd 0b reserved table 24. setting rules for interrupt latch register input conditions resultant value of latch register bit register read data returned in current clock cycle interrupt latch bit is to be set in current clock cycle no no 0 no yes 1 ye s n o 0 ye s ye s 0
ulpi registers stulpi01a, stulpi01b 38/44 doc id 14817 rev 4 note: address 15h(read-only) indicates the current value of various signals useful for debugging. note: address 16h-18h(read), 16h(write), 17h(set), 18h(clear). note: address 19h-1bh(read), 19h(write), 1ah(set), 1bh(clear). table 25. debug register field name bits access reset description linestate0 0 rd 0b contains the current value of linestate(0) linestate1 1 rd 0b contains the current value of linestate(1) reserved 7:2 rd 0b reserved table 26. scratch register field name bits access reset description scratch 7:0 rd/wr/s/c 00b empty register byte for testing purposes. the software can read, write, set, and clear this register and the stulpi01 functionality is not affected. table 27. car kit control register field name bits access reset description reserved 0rd/wr/s/c 0b reserved 1rd/wr/s/c 0b txden 2 rd/wr/s/c 0b enables txd signal in car kit mode rxden 3 rd/wr/s/c 0b enables rxd signal in car kit mode reserved 4rd/wr/s/c 0b reserved 5rd/wr/s/c 0b reserved 6rd/wr/s/c 0b reserved 7rd/wr/s/c 0b
stulpi01a, stulpi01b package mechanical data doc id 14817 rev 4 39/44 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark.
package mechanical data stulpi01a, stulpi01b 40/44 doc id 14817 rev 4 figure 13. tfbga36 package outline table 28. tfbga36 mechanical data " s ymbol l i m . m m s . min. typ. max. min. typ. max. a 0.9 3 3 6.6 3 . 3 4 3 .7 5 2 . 0 1 a 9. 8 a2 0.7 8 0. 8 6 3 0.7 33 .9 b 0.25 0. 3 00. 3 59. 8 11. 8 1 3 . 8 d 3 .5 3 .6 3 .7 1 3 7. 8 141.7 145.7 5 . 2 1 d 9 8 .4 e 3 .5 3 .6 3 .7 1 3 7. 8 141.7 145.7 5 . 2 1 e 9 8 .4 1 5 . 0 e 9.7 7 . 1 2 5 5 . 0 f 1.1 1.11 0.15 5.9 dimen s ion s
stulpi01a, stulpi01b package mechanical data doc id 14817 rev 4 41/44 figure 14. tape and reel tfbga36 package outline 1. drawing not to scale. table 29. tape and reel tfbga36 mechanical data 4a2 4&"'! s ymbol . h c n i . m m min. typ. max. min. typ. max. a 33 . 2 1 0992 c 12. 8 1 3 1 5 . 0 4 0 5 . 0 2 .9 7 . 0 2 . 0 2 d95 . 2 0 6 n 3 62 7 6 5 . 0 4 . 4 1 t ao 3 .9 0.154 bo 3 .9 0.154 5 0 . 0 0 5 . 1 o k 9 po 3 .9 1 6 1 . 0 4 5 1 . 0 1 . 4 p7. 8 9.10. 3 . 0 1 1 3 19 dimen s ion s
order codes stulpi01a, stulpi01b 42/44 doc id 14817 rev 4 10 order codes table 30. order codes order code key differences package packaging stulpi01atbr (1) 1. all these versions need a digital external clock on the xi pin; the xo pin must be left floating or grounded (crystal is not supported). f osc = 19.2 mhz, csn/pwrdn = 0 ?on? tfbga36 (3.6 x 3.6 mm typ.) 3000 parts per reel stulpi01btbr (1) f osc = 26 mhz, csn/pwrdn = 0 ?on? tfbga36 (3.6 x 3.6 mm typ.) 3000 parts per reel
stulpi01a, stulpi01b revision history doc id 14817 rev 4 43/44 11 revision history table 31. document revision history date revision changes 20-jun-2008 1 first release. 24-sep-2010 2 replaced ?iv8vio? with ?dvio? throughout datasheet; updated table 2 , 3 , 5 , 7 ; updated ecopack ? text in section 9 ; reformatted document, minor textual changes. 26-jan-2011 3 updated ta b l e 2 , 3 , 12 ; updated pin name to v dvio throughout document; minor formatting changes. 07-jun-2012 4 updated section 9 (data in ta b l e 2 8 , titles of figure 13 and figure 14 , ta b l e 2 8 and ta b l e 2 9 ), minor text corrections throughout document.
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